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From: yasu@hike.te.chiba-u.ac.jp (Yasunobu Suzuki)
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Subject: [doc-jp 566] dma.sgml =?ISO-2022-JP?B?GyRCQ2YkTkx1JEskRCQkJEYbKEI=?=
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$BNkLZ!w@iMUBg3X$G$9!#(B

$B:#Bg5^$.$G(Bdma.sgml$B$NLu$r9T$J$C$F$$$^$9$,!";d$K$ONI$/$o$+$i$J$$FbMF$G(B
$B$+$J$j6lO+$7$F$$$^$9!#(B

$BFC$K!"0J2<$NItJ,$r$I$N$h$&$KLu$7$?$iNI$$$N$+!"$^$?!"$I$N$h$&$J$3$H$r(B
$B8@$C$F$$$k$N$+65$($FD:$-$?$$$H;W$$$^$9!#$h$m$7$/$*4j$$CW$7$^$9!#(B

90$B9TL\$"$?$j$+$i(B

	      Now all of the signals normally generated by the
	CPU (-MEMR, -MEMW, -IOR, -IOW and a few others) are
	placed in a tri-stated condition (neither high or low)
		    ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^$B$3$NItJ,(B
	and then the CPU asserts the HLDA signal which tells the
	DMA controller that it is now in charge of the bus.  

131$B9TL\$"$?$j$+$i(B
				      If none of the channels
	have their DRQ lines asserted, the DMA controller has
	completed its work and will now tri-state the -MEMR,
					^^^^^^^^^$B$3$NItJ,(B
	-MEMW, -IOR, -IOW and address signals.

$BMW$9$k$K!"(B"tri-state"$B$N0UL#$,NI$/$o$+$i$J$$$N$G$9!#(B
$B!:@Z$.$j$.$j$K?=$7Lu$"$j$^$;$s$,$I$&$>CN7C$r$*B_$72<$5$$!#(B

$B!t(B $B<+J,$N1Q8lNO$N$J$5$K$3$N%W%m%8%'%/%H$K;22C$7$?$3$H$r$A$g$C$H8e2y$7$F$$$k(B...

|    $B@iMUBg3X(B $B9)3X8&5f2J(B $BEE5$EE;R9)3X@l96(B |
|     $BEE;R%7%9%F%`9V:B(B $B7W;;5!9)3XJ,Ln(B(10) |
|           $BNkLZ(B $B9/=$(B ( Suzuki Yasunobu ) |
|       e-mail:yasu@hike.te.chiba-u.ac.jp |
| http://yasu.hike.te.chiba-u.ac.jp/~yasu/|
