From owner-FreeBSD-users-jp@jp.freebsd.org  Tue Jul  7 11:57:31 1998
Received: (from daemon@localhost)
	by jaz.jp.freebsd.org (8.8.8+3.0Wbeta13/8.7.3) id LAA06011;
	Tue, 7 Jul 1998 11:57:31 +0900 (JST)
	(envelope-from owner-FreeBSD-users-jp@jp.FreeBSD.org)
Received: from rocky.kais.kyoto-u.ac.jp (rocky.kais.kyoto-u.ac.jp [130.54.60.156])
	by jaz.jp.freebsd.org (8.8.8+3.0Wbeta13/8.7.3) with ESMTP id LAA06006
	for <FreeBSD-users-jp@jp.freebsd.org>; Tue, 7 Jul 1998 11:57:30 +0900 (JST)
	(envelope-from kaho@rocky.kais.kyoto-u.ac.jp)
Received: from rocky.kais.kyoto-u.ac.jp (localhost [127.0.0.1])
	by rocky.kais.kyoto-u.ac.jp (8.9.0/3.6W) with ESMTP id LAA22273
	for <FreeBSD-users-jp@jp.freebsd.org>; Tue, 7 Jul 1998 11:57:28 +0900 (JST)
Message-Id: <199807070257.LAA22273@rocky.kais.kyoto-u.ac.jp>
To: FreeBSD-users-jp@jp.freebsd.org
In-reply-to: Your message of "Tue, 07 Jul 1998 02:18:44 JST"
References: <199807061718.AA00021@yyutaka.ff.iij4u.or.jp> 
Mime-Version: 1.0 (generated by tm-edit 7.106)
Content-Type: text/plain; charset=ISO-2022-JP
Date: Tue, 07 Jul 1998 11:57:28 +0900
From: KAHO Toshikazu <kaho@rocky.kais.kyoto-u.ac.jp>
Reply-To: FreeBSD-users-jp@jp.freebsd.org
Precedence: bulk
X-Distribute: distribute [version 2.1 (Alpha) patchlevel=24e+ JFUG special]
X-Sequence: FreeBSD-users-jp 30505
Subject: [FreeBSD-users-jp 30505] Re: about MH2-MX233-N 
Errors-To: owner-FreeBSD-users-jp@jp.freebsd.org
Sender: owner-FreeBSD-users-jp@jp.freebsd.org

  $B2<J]!w5~Bg$G$9!#(B

> $B$H$$$&$N$O!">e5-$N?9ED$5$s$,$+$+$l$?!"(Binitcpu.c$B$NJQ99$H$*$J$8$3$H$G$9$+!)(B
> $B$=$l$H$b!"$=$l$G$b!"$&$^$/$J$$$h$H$$$&$3$H$J$N$G$7$g$&$+!)(B  >$B2<J]$5$s(B

  $B$3$l$O!"(BCPU_UPGRADE_HW_CACHE$B$H$O4X78$J$/!"(BVideo$B$N(BMMIO$B$r(BCache$B$7(B
$B$F$7$^$C$F$$$k$N$G$O$J$$$+$H;W$$$^$9!#(B

  2.2.6$B$8$c$J$/$F!"(B3.0-CURRENT$BMQ$N(Bpatch$B$J$s$G$9$,!"$3$s$J$N$rEv(B
$B$F$F$^$9!#(Binitcpu.c$B$NJ}$O$=$N$^$^Ev$?$k$+$b$7$l$^$;$s$,!"(B
options.pc98$B$NJ}$O<j$GEv$F$J$$$H$@$a$@$m$J!#(B

  config file $B$K$O!"(B

options CPU_SUSP_HLT
options CPU_WT_ALLOC
options CPU_UPGRADE_HW_CACHE	# $B$?$V$sL54X78(B
options CPU_CYRIX_WG
options CPU_CYRIX_CACHE_SIZE=ARR_SIZE_1M	# 64MB Memory

$B$rIU$1$F$^$9!#(B``CPU_CYRIX_CACHE_SIZE=''$B$NItJ,$K$O%a%b%j$N<BAuNL(B
$B$K9g$o$;$F!"(B16MB$B$N;~$O(B7$B!"(B32MB$B$N;~$O(B8$B!"(B64MB$B$N;~$O(B9$B!"$C$FIw$K;XDj(B
$B$7$^$9!#(B

  $B$$$A$*$&(BMGA-2064W$B$G(BX$B$,F0$$$F$^$9!#(BTrident 9680XGI $B$O!"(BM1$B$rF~$l(B
$B$F$$$?:"$OF0$$$F$?$1$I!":G6a$O;n$7$F$J$$$G$9!#(B

------ $B$3$3$+$i(B
--- i386/i386/initcpu.c.orig	Sat May 16 23:38:10 1998
+++ i386/i386/initcpu.c	Mon Jul  6 00:47:19 1998
@@ -339,6 +339,34 @@
 	write_cyrix_reg(CCR5, read_cyrix_reg(CCR5) | CCR5_WT_ALLOC);
 #endif
 
+#ifdef CPU_CYRIX_CACHE_SIZE
+	/* set cache size ARR7 and RCR7 */
+	write_cyrix_reg(ARR7, 0);
+	write_cyrix_reg(ARR7+1, 0);
+	write_cyrix_reg(ARR7+2, CPU_CYRIX_CACHE_SIZE & 0x0f);
+	write_cyrix_reg(RCR7, read_cyrix_reg(RCR7) | RCR_RCE);
+#ifdef PC98
+	if(!(inb(0x43b)&4)) 
+	  {
+	    /* if port 0x43b bit2 is 0, */
+	    /* memory is not mapped 15-16M region */
+	    /* disable 15-16M memory region cache */
+	    write_cyrix_reg(ARR0,0);
+	    write_cyrix_reg(ARR0+1,0xf0);
+	    write_cyrix_reg(ARR0+2,ARR_SIZE_1M);
+	    write_cyrix_reg(RCR0, RCR_RCD);
+	  }
+#endif
+	/* set CCR5 to enable ARR register */
+	write_cyrix_reg(CCR5, read_cyrix_reg(CCR5) | CCR5_ARREN);
+#endif
+
+#ifdef CPU_CYRIX_WG
+	/* only if ARR7 is enabled */
+	if (read_cyrix_reg(RCR7) & RCR_RCE )
+	  write_cyrix_reg(RCR7, read_cyrix_reg(RCR7) | RCR_WG | RCR_WWO );
+#endif
+
 	/* Restore CCR3. */
 	write_cyrix_reg(CCR3, ccr3);
 
@@ -419,6 +447,34 @@
 	/* Initialize CCR5. */
 #ifdef CPU_WT_ALLOC
 	write_cyrix_reg(CCR5, read_cyrix_reg(CCR5) | CCR5_WT_ALLOC);
+#endif
+
+#ifdef CPU_CYRIX_CACHE_SIZE
+	/* set cache size ARR7 and RCR7 */
+	write_cyrix_reg(ARR7, 0);
+	write_cyrix_reg(ARR7+1, 0);
+	write_cyrix_reg(ARR7+2, CPU_CYRIX_CACHE_SIZE & 0x0f);
+	write_cyrix_reg(RCR7, read_cyrix_reg(RCR7) | RCR_RCE);
+#ifdef PC98
+	if(!(inb(0x43b)&4)) 
+	  {
+	    /* if port 0x43b bit2 is 0, */
+	    /* memory is not mapped 15-16M region */
+	    /* disable 15-16M memory region cache */
+	    write_cyrix_reg(ARR0,0);
+	    write_cyrix_reg(ARR0+1,0xf0);
+	    write_cyrix_reg(ARR0+2,ARR_SIZE_1M);
+	    write_cyrix_reg(RCR0, RCR_RCD);
+	  }
+#endif
+	/* set CCR5 to enable ARR register */
+	write_cyrix_reg(CCR5, read_cyrix_reg(CCR5) | CCR5_ARREN);
+#endif
+
+#ifdef CPU_CYRIX_WG
+	/* only if ARR7 is enabled */
+	if (read_cyrix_reg(RCR7) & RCR_RCE )
+	  write_cyrix_reg(RCR7, read_cyrix_reg(RCR7) | RCR_WG | RCR_WWO );
 #endif
 
 	/* Restore CCR3. */
--- pc98/conf/options.pc98.orig	Sat Jul  4 18:44:16 1998
+++ pc98/conf/options.pc98	Mon Jul  6 00:47:32 1998
@@ -54,6 +54,8 @@
 CPU_BLUELIGHTNING_FPU_OP_CACHE	opt_cpu.h
 CPU_BLUELIGHTNING_3X		opt_cpu.h
 CPU_BTB_EN			opt_cpu.h
+CPU_CYRIX_WG			opt_cpu.h
+CPU_CYRIX_CACHE_SIZE		opt_cpu.h
 CPU_DIRECT_MAPPED_CACHE		opt_cpu.h
 CPU_DISABLE_5X86_LSSER		opt_cpu.h
 CPU_FASTER_5X86_FPU		opt_cpu.h
@@ -63,6 +65,7 @@
 CPU_RSTK_EN			opt_cpu.h
 CPU_SUSP_HLT			opt_cpu.h
 CPU_UPGRADE_HW_CACHE		opt_cpu.h
+CPU_WT_ALLOC			opt_cpu.h
 CYRIX_CACHE_WORKS		opt_cpu.h
 CYRIX_CACHE_REALLY_WORKS	opt_cpu.h
------ $B$3$3$^$G(B
kaho@elam.kais.kyoto-u.ac.jp
