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To: FreeBSD-users-jp@jp.FreeBSD.org
From: FUJITA Kazutoshi <fujita@soum.co.jp>
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Subject: [FreeBSD-users-jp 70210] Re: Failed to attach NIC: SiS900 on
 K7S5A (work around)
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From: SHIRAISHI Kei-ichi <siraisi@dc.takuma-ct.ac.jp>
Subject: [FreeBSD-users-jp 70208] Re: Failed to attach NIC: SiS900 on K7S5A (work around)
Date: Mon, 12 Aug 2002 15:44:53 +0900
Message-ID: <20020812.154453.730552577.shira@dc.takuma-ct.ac.jp>

> $B$"$l$+$i!"(BWindowsXP, RedHat Linux7.3$B$r%$%s%9%H!<%k$7$F$_$^$7$?!#(B
> $B$I$A$i$G$bF0$-$^$7$?!#(B
> Linux$B$N(Bdmesg$B$O0J2<$NDL$j$G$9!#(B($B<j$G<L$7$F$$$k$N$G4V0c$$$,$"$k$+$b(B)
> 
> eth0: Realtek RTL8201 PHY tranceiver found at address 1.
> eth0: Using tranceiver found at address 1 as default
> eth0: SiS 900 PCI Fast Ethernet at 0xd400, IRQ 5, 00:50:eb:04:6a:34.
> eth0: Media Link On 100mbps full-duplex
> 
> $B$3$l$rF0$+$9$N$K!"2?$+NI$$J}K!$O$"$j$^$;$s$+!)(B

$B$3$l$C$F!"$b$7$+$7$F(BSiS 650$B%A%C%W%;%C%H$N%d%D$G$9$+$M!)(B
$B$\$/$b(B2$B%v7n$/$i$$A0$K(BSiS 650$B$N(BPC$B$rGc$C$?$N$G$9$,!"$d$C$Q$j(BSiS900$B$,(B
$BF0$-$^$;$s$G$7$?!#(B

$B$A$g$C$HD4$Y$F$_$?$N$G$9$,!"(BENPHY(Enhanced PHY Access Register)$B$H(B
$B$$$&%l%8%9%?<~$j$,%U%D!<$N(BSiS900$B$H$O$A$g$C$H0c$&$_$?$$$G$9!#(B

Linux$B$G$OF0$$$?$N$G!"%I%i%$%P$r8+$F$_$?$N$G$9$,!"(BLinux$B$N%I%i%$%P(B
$B$G$O(BPHY$B$X$N%"%/%;%9$K$O!"<B$O$3$N%l%8%9%?$r;HMQ$7$F$*$i$:!"(B
$B%7%j%"%k(BIO$B$r$d$C$F$^$7$?!#(B

ENPHY$B<~$j$r$$$m$$$mD4$Y$F$kM>M5$b$J$+$C$?$N$G!"$H$F$b8e8~$-$J2r7h(B
$B$@$H$O;W$&$N$G$9$,!"%7%j%"%k(BIO$B$r<BAu$7$F$_$?$b$N$,$"$j$^$9!#(B
$B$h$m$7$1$l$P$I$&$>!#(B($B$b$A$m$s(Bat your own risk$B$H$$$&$3$H$G(B;-p)


--($B$U(B)

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*** /sys/pci/if_sisreg.h	Thu Feb 28 14:39:32 2002
--- if_sisreg.h	Mon Jul  1 00:19:19 2002
***************
*** 124,129 ****
--- 124,151 ----
  #define SIS_EECMD_READ		0x180
  #define SIS_EECMD_ERASE		0x1c0
  
+ #define	SIS_NOENPHY	/* don't use Enhanced PHY Access Register */
+ #ifdef	SIS_NOENPHY
+ #define	SIS_MII_FRAME_START	0x4000
+ #define	SIS_MII_FRAME_OP_READ	0x2000
+ #define	SIS_MII_FRAME_OP_WRITE	0x1000
+ #define	SIS_MII_FRAME_PMD(phy)	((phy & 0x1F) << 7)
+ #define	SIS_MII_FRAME_REG(reg)	((reg & 0x1F) << 2)
+ #define	SIS_MII_FRAME_LINE_READ	0x0000
+ #define	SIS_MII_FRAME_LINE_WRITE	0x0002
+ #define SIS_MII_FRAME_READ(phy, reg)				\
+ 	(SIS_MII_FRAME_START | SIS_MII_FRAME_OP_READ		\
+ 	 | SIS_MII_FRAME_PMD(phy) | SIS_MII_FRAME_REG(reg)	\
+ 	 | SIS_MII_FRAME_LINE_READ)
+ #define SIS_MII_FRAME_WRITE(phy, reg)				\
+ 	(SIS_MII_FRAME_START | SIS_MII_FRAME_OP_WRITE		\
+ 	 | SIS_MII_FRAME_PMD(phy) | SIS_MII_FRAME_REG(reg)	\
+ 	 | SIS_MII_FRAME_LINE_WRITE)
+ #define	SIS_MII_MDC		0x00000040
+ #define	SIS_MII_MDDIR		0x00000020
+ #define	SIS_MII_MDIO		0x00000010
+ #endif	/* SIS_NOENPHY */
+ 
  #define SIS_EE_NODEADDR		0x8
  #define NS_EE_NODEADDR		0x6
  
*** /sys/pci/if_sis.c	Thu Feb 28 14:39:32 2002
--- if_sis.c	Mon Jul  1 00:11:11 2002
***************
*** 475,480 ****
--- 475,483 ----
  {
  	struct sis_softc	*sc;
  	int			i, val = 0;
+ #ifdef	SIS_NOENPHY
+ 	int			frame_hdr = SIS_MII_FRAME_READ(phy, reg);
+ #endif
  
  	sc = device_get_softc(dev);
  
***************
*** 501,506 ****
--- 504,536 ----
  	    sc->sis_rev < SIS_REV_635 && phy != 0)
  		return(0);
  
+ #ifdef	SIS_NOENPHY
+ 	sis_eeprom_idle(sc);
+ 
+ 	for (i = (1 << 15); i; i >>= 1) {
+ 		int dataval = SIS_MII_MDDIR;
+ 		if (frame_hdr & i) {
+ 			dataval |= SIS_MII_MDIO;
+ 		}
+ 		CSR_WRITE_4(sc, SIS_EECTL, dataval);
+ 		sis_delay(sc);
+ 		CSR_WRITE_4(sc, SIS_EECTL, (dataval | SIS_MII_MDC));
+ 		sis_delay(sc);
+ 	}
+ 
+ 	for (i = (1 << 15); i; i >>= 1) {
+ 		CSR_WRITE_4(sc, SIS_EECTL, 0);
+ 		sis_delay(sc);
+ 		if (CSR_READ_4(sc, SIS_EECTL) & SIS_MII_MDIO) {
+ 			val |= i;
+ 		}
+ 		CSR_WRITE_4(sc, SIS_EECTL, SIS_MII_MDC);
+ 		sis_delay(sc);
+ 	}
+ 	CSR_WRITE_4(sc, SIS_EECTL, 0);
+ 
+ 	sis_eeprom_idle(sc);
+ #else	/* SIS_NOENPHY */
  	CSR_WRITE_4(sc, SIS_PHYCTL, (phy << 11) | (reg << 6) | SIS_PHYOP_READ);
  	SIS_SETBIT(sc, SIS_PHYCTL, SIS_PHYCTL_ACCESS);
  
***************
*** 518,523 ****
--- 548,554 ----
  
  	if (val == 0xFFFF)
  		return(0);
+ #endif	/* SIS_NOENPHY */
  
  	return(val);
  }
***************
*** 528,533 ****
--- 559,567 ----
  {
  	struct sis_softc	*sc;
  	int			i;
+ #ifdef	SIS_NOENPHY
+ 	int			frame_hdr = SIS_MII_FRAME_WRITE(phy, reg);
+ #endif	/* SIS_NOENPHY */
  
  	sc = device_get_softc(dev);
  
***************
*** 538,546 ****
  		return(0);
  	}
  
! 	if (sc->sis_type == SIS_TYPE_900 && phy != 0)
  		return(0);
  
  	CSR_WRITE_4(sc, SIS_PHYCTL, (data << 16) | (phy << 11) |
  	    (reg << 6) | SIS_PHYOP_WRITE);
  	SIS_SETBIT(sc, SIS_PHYCTL, SIS_PHYCTL_ACCESS);
--- 572,618 ----
  		return(0);
  	}
  
! 	if (sc->sis_type == SIS_TYPE_900 &&
! 	    sc->sis_rev < SIS_REV_635 && phy != 0)
  		return(0);
  
+ #ifdef	SIS_NOENPHY
+ 	sis_eeprom_idle(sc);
+ 
+ 	for (i = (1 << 15); i; i >>= 1) {
+ 		int dataval = SIS_MII_MDDIR;
+ 		if (frame_hdr & i) {
+ 			dataval |= SIS_MII_MDIO;
+ 		}
+ 		CSR_WRITE_4(sc, SIS_EECTL, dataval);
+ 		sis_delay(sc);
+ 		CSR_WRITE_4(sc, SIS_EECTL, (dataval | SIS_MII_MDC));
+ 		sis_delay(sc);
+ 	}
+ 	sis_delay(sc);
+ 
+ 	for (i = (1 << 15); i; i >>= 1) {
+ 		int dataval = SIS_MII_MDDIR;
+ 		if (data & i) {
+ 			dataval |= SIS_MII_MDIO;
+ 		}
+ 		CSR_WRITE_4(sc, SIS_EECTL, dataval);
+ 		sis_delay(sc);
+ 		CSR_WRITE_4(sc, SIS_EECTL, (dataval | SIS_MII_MDC));
+ 		sis_delay(sc);
+ 	}
+ 	sis_delay(sc);
+ 
+ 	for (i = 2; i > 0; i --) {
+ 		CSR_WRITE_4(sc, SIS_EECTL, 0);
+ 		sis_delay(sc);
+ 		CSR_WRITE_4(sc, SIS_EECTL, SIS_MII_MDC);
+ 		sis_delay(sc);
+ 	}
+ 	CSR_WRITE_4(sc, SIS_EECTL, 0);
+ 
+ 	sis_eeprom_idle(sc);
+ #else	/* SIS_NOENPHY */
  	CSR_WRITE_4(sc, SIS_PHYCTL, (data << 16) | (phy << 11) |
  	    (reg << 6) | SIS_PHYOP_WRITE);
  	SIS_SETBIT(sc, SIS_PHYCTL, SIS_PHYCTL_ACCESS);
***************
*** 552,557 ****
--- 624,630 ----
  
  	if (i == SIS_TIMEOUT)
  		printf("sis%d: PHY failed to come ready\n", sc->sis_unit);
+ #endif	/* SIS_NOENPHY */
  
  	return(0);
  }

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