* CGDR test
sysclear
archmode esame
r 1a0=00000001800000000000000000000200 # z/Arch restart PSW
r 1d0=00020001800000000000000000BADBAD # z/Arch pgm new PSW
r 200=B7000330     # LCTL R0,R0,CTLR0  Set CR0 bit 45
r 204=B29D0334     # LFPC FPCREG       Load FPC register
r 208=41000008     # LA R0,8           R0=Number of test data
r 20C=41100800     # LA R1,TEST1       R1=>Test data table
r 210=41F00900     # LA R15,RES1       R15=>Result table
r 214=68401000     #A LD F4,0(,R1)     Load FPR4=TESTn
r 218=41200000     # LA R2,X'00'       R2=Rounding mode
r 21C=42200222     #B STC R2,I+2       Store rounding mode into instr
r 220=B3C90074     #I CGDR R7,0,F4     Convert FPR4 into R7
r 224=B2220080     # IPM R8            R8=Cond code and pgm mask
r 228=5890008C     # L R9,PGMINTC      R9=PGM check interrupt code
r 22C=E370F0000024 # STG R7,0(,R15)    Store R7 in result table
r 232=9089F008     # STM R8,R9,8(R15)  Store CC and PIC in table
r 236=41F0F010     # LA R15,16(,R15)   R15=>next result table
r 23A=EC270005107F # CLIJNE R2,X'10',*+10  Skip if not rounding mode 1
r 240=41202020     # LA R2,X'20'(R2)   Bypass rounding modes 2 and 3
r 244=41202010     # LA R2,X'10'(R2)   R2=Next rounding mode
r 248=EC24021C80FF # CLIBL R2,X'80',B  Loop if rounding mode less than 8
r 24E=41101008     # LA R1,8(,R1)      R1=>Next TESTn
r 252=46000214     # BCT R0,A          Loop to end of TEST table
r 256=41000900     # LA R0,RES1        R0->Actual results
r 25A=41100300     # LA R1,48*16       R1=Length of results table
r 25E=41200C00     # LA R2,EXP1        R2->Expected results
r 262=41300300     # LA R3,48*16       R3=Length of results table
r 266=0F02         # CLCL R0,R2        Compare with expected results
r 268=477002FC     # BNE DIE           Error if not equal
r 26C=B2B20300     # LPSWE WAITPSW     Load enabled wait PSW
r 2FC=B2B20310     # LPSWE DISWAIT     Load disabled wait PSW
r 300=07020001800000000000000000AAAAAA # WAITPSW Enabled wait state PSW
r 310=00020001800000000000000000BADBAD # DISWAIT Disabled wait state PSW
r 320=00000001800000000000000000000340 # NEWPSWI New PSW for PGMFLIH
r 330=00040000     # CTLR0             Control register 0 (bit45 AFP control)
r 334=00000000     # FPCREG            Floating point control register
r 340=B2B20150     #PGMFLIH LPSWE PGMOPSW  Program check interrupt handler
r 800=D080000000000000                 # TEST1 DC DH'-9223372036854775808'
r 808=D07FFFFFFFFFFFFF                 # TEST2 DC DH'-9223372036854775652'
r 810=C27B800000000000                 # TEST3 DC DH'-123.5'
r 818=8000000000000000                 # TEST4 DC DH'-0'
r 820=427A800000000000                 # TEST5 DC DH'122.5'
r 828=487FFFFFFF800000                 # TEST6 DC DH'2147483648.5'
r 830=507FFFFFFFFFFFFF                 # TEST7 DC DH'9223372036854775652'
r 838=5080000000000000                 # TEST8 DC DH'9223372036854775808'
* Expected results - TEST1
r C00=80000000000000001000000000000000
r C10=80000000000000001000000000000000
r C20=80000000000000001000000000000000
r C30=80000000000000001000000000000000
r C40=80000000000000001000000000000000
r C50=80000000000000001000000000000000
* Expected results - TEST2
r C60=80000000000001001000000000000000
r C70=80000000000001001000000000000000
r C80=80000000000001001000000000000000
r C90=80000000000001001000000000000000
r CA0=80000000000001001000000000000000
r CB0=80000000000001001000000000000000
* Expected results - TEST3
r CC0=FFFFFFFFFFFFFF851000000000000000
r CD0=FFFFFFFFFFFFFF841000000000000000
r CE0=FFFFFFFFFFFFFF841000000000000000
r CF0=FFFFFFFFFFFFFF851000000000000000
r D00=FFFFFFFFFFFFFF851000000000000000
r D10=FFFFFFFFFFFFFF841000000000000000
* Expected results - TEST4
r D20=00000000000000000000000000000000
r D30=00000000000000000000000000000000
r D40=00000000000000000000000000000000
r D50=00000000000000000000000000000000
r D60=00000000000000000000000000000000
r D70=00000000000000000000000000000000
* Expected results - TEST5
r D80=000000000000007A2000000000000000
r D90=000000000000007B2000000000000000
r DA0=000000000000007A2000000000000000
r DB0=000000000000007A2000000000000000
r DC0=000000000000007B2000000000000000
r DD0=000000000000007A2000000000000000
* Expected results - TEST6
r DE0=000000007FFFFFFF2000000000000000
r DF0=00000000800000002000000000000000
r E00=00000000800000002000000000000000
r E10=000000007FFFFFFF2000000000000000
r E20=00000000800000002000000000000000
r E30=000000007FFFFFFF2000000000000000
* Expected results - TEST7
r E40=7FFFFFFFFFFFFF002000000000000000
r E50=7FFFFFFFFFFFFF002000000000000000
r E60=7FFFFFFFFFFFFF002000000000000000
r E70=7FFFFFFFFFFFFF002000000000000000
r E80=7FFFFFFFFFFFFF002000000000000000
r E90=7FFFFFFFFFFFFF002000000000000000
* Expected results - TEST8
r EA0=7FFFFFFFFFFFFFFF3000000000000000
r EB0=7FFFFFFFFFFFFFFF3000000000000000
r EC0=7FFFFFFFFFFFFFFF3000000000000000
r ED0=7FFFFFFFFFFFFFFF3000000000000000
r EE0=7FFFFFFFFFFFFFFF3000000000000000
r EF0=7FFFFFFFFFFFFFFF3000000000000000
ostailor null
restart
pause 1
* Display test data
r 800.40
* Display results - TEST1
r 900.60
* Display results - TEST2
r 960.60
* Display results - TEST3
r 9C0.60
* Display results - TEST4
r A20.60
* Display results - TEST5
r A80.60
* Display results - TEST6
r AE0.60
* Display results - TEST7
r B40.60
* Display results - TEST8
r BA0.60
