cad/MyHDL-iverilog/Makefile:	$NetBSD: Makefile,v 1.10 2016/10/09 03:15:57 kamil Exp $
cad/MyHDL-iverilog/PLIST:	$NetBSD: PLIST,v 1.2 2016/10/09 03:15:57 kamil Exp $
cad/py-MyHDL/patches/patch-cosimulation_cver_Makefile.lnx:	$NetBSD: patch-cosimulation_cver_Makefile.lnx,v 1.1 2022/05/03 17:38:34 nia Exp $
cad/py-MyHDL/patches/patch-myhdl___always__seq.py:	$NetBSD: patch-myhdl___always__seq.py,v 1.1 2018/12/27 16:01:54 joerg Exp $
cad/py-MyHDL/patches/patch-myhdl_conversion___toVHDL.py:	$NetBSD: patch-myhdl_conversion___toVHDL.py,v 1.1 2018/12/27 16:01:54 joerg Exp $
