##
## makerule --- rules for makefiles
##

##
# variables
#
AS  := $(CROSS)as
CC  := $(CROSS)gcc
CPP := $(CC) -E
AR  := $(CROSS)ar
LD  := $(CROSS)ld
HOST_CC := gcc
CFLAGS  := -I$(TOPDIR)/inc -I$(TOPDIR)/$(ARCH) -I. -O2 -Wall

##
# setup
#
.PHONY: FORCE
DIRS= $(dir)
OBJS= $(obj)
DEPS= $(dep) $(patsubst %.o,%.dep,$(filter %.o,$(OBJS)))
all: $(first) $(DIRS) $(DEPS) $(arc) $(last)

##
# include dependency rules
#
ifneq "$(DEPS)" ""
  sinclude $(DEPS)
endif

##
# recursively make
#
RELDIR ?= .
$(DIRS): FORCE
	@$(MAKE) RELDIR=$(RELDIR)/$@ -C$@
%/: FORCE
	@$(MAKE) RELDIR=$(RELDIR)/$* -C$*

##
# compile a set of .o files into one .a file
#
ifdef arc
$(arc): $(OBJS)
	@echo LD $(RELDIR)/$@
	@rm -f $@
  ifneq "$(strip $(OBJS))" ""
	@$(LD) $(LDFLAGS) $(EX_LDFLAGS) -r $(filter $(OBJS), $^) -o $@
  else
	@$(AR) rcs $@
  endif
endif

##
# common rules
#
%.o: %.c
	@echo CC $(RELDIR)/$@
	@$(CC) $(CFLAGS) $(EX_CFLAGS) $(CFLAGS_$@) -c -o $@ $<

%.dep: %.c
	@echo DEP $(RELDIR)/$@
	@$(CPP) $(CFLAGS) $(EX_CFLAGS) $(CFLAGS_$@) -M -MG $< > $@

%.o: %.S
	@echo CC $(RELDIR)/$@
	@$(CC) $(AFLAGS) $(EX_AFLAGS) $(AFLAGS_$@) -c -o $@ $<

%.s: %.c
	@echo CC $(RELDIR)/$@
	@$(CC) $(CFLAGS) $(EX_CFLAGS) $(CFLAGS_$@) -S -o $@ $<
